| Resource | Parameter | Value | Remarks |
|---|---|---|---|
| ADC | VREF | 1.2 V | |
| Measurement type | Single Ended | ||
| Input voltage range | 0 to 2.4 V (0 to 2*VREF) | ||
| Output range | 0x000 to 0x7FF | ||
| DAC | Reference source | VDDA | |
| Input range | 0x000 to 0xFFF | ||
| Output range | 0 to VDDA | ||
| Output type | Unbuffered output | ||
| I2C | Role | Master | Configurable to slave mode through HAL function |
| Data rate | 100 kbps | Configurable through HAL function | |
| Drive mode of SCL & SDA pins | Open Drain (drives low) | External pull-up resistors are required | |
| LpTimer | Uses WCO (32.768 kHz) as clock source & MCWDT as counter; 1 count = 1/32768 second or 32768 counts = 1 second | ||
| SPI | Data rate | 100 kpbs | Configurable through HAL function |
| Slave select polarity | Active low | ||
| UART | Flow control | No flow control | Configurable through HAL function |
| Data format | 8N1 | Configurable through HAL function | |
| Baud rate | 115200 | Configurable through HAL function | |
| OPAMP,COMP | Pin (P9_3) | Always 0 V | R131 is not soldered by default |
| LPCOMP | Pins (P8_2, P8_3) | Always 0 V | R103, R99 are not soldered by default |
Pins P24 through P24_4, P25_0 through P25_7, and P32_0 through P32_6 should not be driven with pull-up drive mode. These pins are used to send signals to the on-board M.2 slot through SMIF, SDIO, and the BT UART Interface. The output of these pins pass through voltage level translators before reaching the M.2 slot. These voltage level translators require a minimum input drive strength of 2mA for the signal to pass through, significantly higher than the 66uA generated when using pull-up drive mode. Strong drive mode is recommended for these pins.
© Cypress Semiconductor Corporation, 2024.